1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor integrated circuit capable of reduction in current consumption, control of the generation of noise, and increase in access speed, using a precharge voltage applied to a precharge circuit.
2. Description of the Related Art
In a semiconductor memory device such as an EEPROM and a DRAM, data input/output lines or bit lines are precharged before data is read out from a memory cell. To set a potential of this precharge is very important for reading data at high speed and decreasing current consumption in the semiconductor memory device.
For example, a power precharge system is used for data I/O lines of a DRAM. In this power precharge system, a pair of data input/output lines IO and IO is precharged at a power supply voltage of 5 V before data is read out from a memory cell. When the data is read out, one of the data input/output lines is discharged from 5 V to 0 V, and a variation in potential of the discharged data input/output line is detected by a sense amplifier.
However, the conventional power precharge system has drawbacks in which current consumption is increased and noise is easy to generate. This is because a data input/output line generally has a relatively large capacitor, and this data input/output line has to be discharged at a full amplitude of the power supply voltage.